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ELKA

SSP

Shift register

ELKA > SSP

SSP

Shift register:

library ieee;
use ieee.std_logic_1164.all;

entity shift_reg is
    port(Din : in std_logic_vector(7 downto 0);
         clk,shift,load,rst : in std_logic;
         dout : out std_logic
    );
end shift_reg;

architecture beh of shift_reg is
    signal tmp : std_logic_vector(7 downto 0);

    begin
        dout <= tmp(0);

        process(clk,rst)
           begin
           if(rst='0') then
               tmp <= (others => '0');
           elsif (rising_edge(clk)) then
               if (load = '0') then
                  tmp <= Din;
               elsif(shift='0')then
                  tmp <= '0' & tmp(7 downto 1);
               end if;
           end if;
        end process;
end;